1. Field of the Invention
The present invention generally relates to integration density enhancements of very large scale integrated (VLSI) circuit devices and, more particularly, to increasing integration density of devices, such as dynamic random access memories (DRAMs), by the use of an angled etch to selectively remove a polysilicon liner from one side of a trench in a manner that prevents one side of a trench from short-circuiting to the adjacent surface strap.
2. Background Description
Current layout rules and manufacturing overlay technology limit the minimum cell width. If layout rules could be enhanced the result would be increased storage cell density for DRAMs. A common trench type DRAM cell configuration requires certain minimum dimensions, in the direction parallel to word lines, for proper connection of the polysilicon trench fill storage node to the node diffusion outside the trench. Currently, there are four critical dimensions (i.e., layout rules) in the manufacture of merged isolation and node trench DRAMs:
the silicon strap overlap outside a deep trench, for node diffusion contact, PA1 the silicon strap overlap inside a deep trench, for polysilicon node contact, PA1 the silicon strap to adjacent diffusion inside a deep trench for no contact to adjacent node diffusion, and PA1 the silicon strap to an adjacent trench for no contact to adjacent trench polysilicon node.
These four dimensions or rules result in a minimum cell width of 0.85 .mu.m, using a contemporary set of layout rules. By application of the usual generation scaling factor of 0.7.times., a strap limited cell width of 0.60 .mu.m is obtained. This is not small enough to meet a 4.times.x higher density objective. A cell width of 0.50 .mu.m to 0.55 .mu.m is needed.